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features applications ? up to 4 emitters and 1 compensator ? automatic calibration of all relevant values ? optical principle with no mechanics ? spi and i 2 c communication interfaces available ? 16 bit microcontroller with 8 mhz clock ? 32 kbyte flash and 3 kbyte sram memory ? 50 a standby current ? 2.5 ma circuit operating current ? supply voltage range core 2.25 v to 2.75 v / io 1.50 v to 2.8 v ? highly intuitive input devices (e.g. handheld devices, hmi steering wheel, 3 d mmis, etc.) ? in combination with suitable optics and additional software, resolves real x, y, z coordinates ( 64 x 64 x 16 positions ) ? navigation keys, rotary switches, sliders, proximity sensors and optical switches ? multi-key applications for rough environmental conditions ? long range (up to 3 m) proximity & motion detection general description the halios? multi purpose optical sensor is based on an optical bridge which provides a contactless detec - tion of gestures (e.g. movement of a fnger). the ic e 909.05 processes data from optical refections of an object in front of the sensor using a system called hal - ios? (high ambient light independent optical system). halios? is highly effcient suppressing ambient light and also has an inherent self calibration capability to eliminate disturbances caused by housing refections such as dirt or scratches. new intuitive user interfaces are possible with this unique input device. all data is analyzed and evaluated internally with a high performance microprocessor and the data output can be easily customized. halios? devices can be applied behind closed surfaces which allows very fexible designs. halios? frmware provides all necessary algorithms and software based flters. ka - + avdd dvdd nrst miso mosi sck cs sda scl gpio 6 reset clock test timer gpio interface i 2 c interface irq control watchdog multiply ram flash spi interface cpu core 16 bit j t a g tmode an vddi sda e909.05 scl tm1 tm0 hvpad led1 led2 led3 led4 ledc halios control digital/ analog ? product id temp. range package e909.05 -40c to +85c qfn32l5 ordering information e909.05 elmos semiconductor ag data sheet qm-no.: 25ds0014e.00 preliminary data sheet - aug 02, 2011 halios? multi-purpose optical sensor with high light immunity 1/67 this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifcations and information herein without notice.
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 1 pinout 1.1 pin description nr. name type pull esd description 1 sda d_io --- +/- 2kv hbm i2c data in/out 2 scl d_io --- +/- 2kv hbm i2c clock input 3 io5 d_io down +/- 2kv hbm multifunctional digital output 5 4 io4 d_io down +/- 2kv hbm multifunctional digital output 4 5 io3 d_io down +/- 2kv hbm multifunctional digital output 3 6 io2 d_io down +/- 2kv hbm multifunctional digital output 2 7 io1 d_io down +/- 2kv hbm multifunctional digital output 1 8 led4 a_o --- +/- 2kv hbm output sending led4 9 ledvss a_g --- +/- 2kv hbm power ground led 10 io0 d_io down +/- 2kv hbm multifunctional digital output 0 11 tmode d_i down +/- 2kv hbm test mode enable 12 nrst d_i up +/- 2kv hbm reset input, active low 13 vssi s --- +/- 2kv hbm ground io pins 14 vddi s --- +/- 2kv hbm supply io pins 15 dvdd s --- +/- 2kv hbm digital supply 16 dvss s --- +/- 2kv hbm digital ground 17 ledvss s --- +/- 2kv hbm power ground led 18 led3 a_o --- +/- 2kv hbm output sending led3 19 ledc a_o --- +/- 2kv hbm output compensation led 20 nc --- --- +/- 2kv hbm --- 21 nc --- --- +/- 2kv hbm --- 22 ca a_i --- +/- 2kv hbm photo diode amplifier input 23 an a_i --- +/- 2kv hbm reference voltage for photo diode 24 led2 a_o --- +/- 2kv hbm output sending led2 25 ledvss s --- +/- 2kv hbm power ground led 26 avss s --- +/- 2kv hbm analogue ground 27 avdd s --- +/- 2kv hbm analogue supply voltage 28 tm1 a_io --- +/- 2kv hbm flash test, analogue test bus 29 tm0 a_io --- +/- 2kv hbm flash test, analogue test bus 30 vpp hv_s --- +/- 2kv hbm flash program voltage 31 led1 a_o --- +/- 2kv hbm output sending led1 32 ledvss s --- +/- 2kv hbm power ground led d = digital, a = analogue, s = supply, i = input, o = output, hv = high voltage (max. 15v ), nc = not connec - ted table 1.1.1 pin description this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 2 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 1.2 package reference the device is available in a pb free, rohs compliant, 20-lead quad flat no lead qfn32l5 package with 25mm2 (0.0388 square inch) according to jedec standard mo-220- k ; variant: vhhd-4. 1.3 package pinout figure 1.3-1 : package pinout this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 3 / 67 qm-no.: 25ds0014e.00 led2 an ca nc nc ledc led3 ledvss d v s s d v d d v d d i v s s i n r s t t m o d e i o 0 l e d v s s 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 sda scl io5 io4 io3 io2 io1 led4 l e d v s s a v s s a v d d t m 1 t m 0 v p p l e d 1 l e d v s s
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 2 block diagram this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 4 / 67 qm-no.: 25ds0014e.00 figure 2-1 block diagram halios ? control digital/analog led1 led2 led3 led4 ledc vddc clock io avdd reset nrst cpu core 16 bit flash ram timer j t a g watchdog spi/sci interface csb i2c interface gpio interface sck mosi miso irq control multiply tmode test 6 vddi vpp tm1 sda scl tm0 filter demod. ca an
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 3 operating conditions 3.1 absolute maximum ratings continuous operation of the device above these ratings is not allowed and may destroy the device. all poten - tials refer to ground (gnd) unless otherwise specified. currents flowing into the circuit pins have positive values. parameter condition symbol min. max. unit supply voltage: digital core, analogue part referenced to d vss / a vss d vss / a vss -0. 3 2.8 v io supply voltage/digital pins (see type/chapter 1.1 ) referenced to v ssi v ddi -0.3 2.8 v input voltage analog pins (see type/chapter 1.1 ) referenced to a vss v ina -0.3 a vdd + 0.3 v input voltage digital pins/gpio (see type/chapter 1.1 ) referenced to v ssi v ind -0.3 v ddi + 0.3 v ground offset d vss to a vss to led vss -0.3 0.3 v junction temperature t j -40 125 c storage temperature t stg -50 150 c table 3.1.1 absolute maximum ratings 3.2 recommended operating conditions the following conditions apply unless otherwise stated. all potentials refer to ground (gnd) unless other - wise specified. currents flowing into the circuit pins have positive values. parameter condition symbol min. typ. max. unit supply voltage: analogue part, digital core referenced to d vss /a vss d vdd /a vdd 2.25 2.5 2.75 v io supply voltage/digital pins (see type/chapter 1.1 ) referenced to v ssi v ddi 1.50 1.8 d vdd v filter capacitor analogue part connected to a vdd c avdd 100 nf filter capacitor digital part connected to d vdd c dvdd 100 nf ambient operating temperature range t opt -40 25 85 c table 3.2.1 recommended operating conditions all voltages are referred to d vss , and currents are positive when flowing into the node unless otherwise spe - cified. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 5 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4 detailed electrical data specification the following conditions apply unless otherwise stated. all potentials refer to ground (gnd) unless other - wise specified. currents flowing into the circuit pins have positive values. 4.1 supply voltages no. parameter condition symbol min. typ. max. unit 1 digital operating current, run mode fsys = 8 mhz, sys - tem state: run i dvdd 5.8 12 ma 2 digital operating current, standby mode system state: standby i standby 1.8 5 ma 3 digital operating current, off mode system state: off i off 35 a 4 analogue operating current analogue on = 1 i avdd 4.5 5.0 ma 5 analogue operating current analogue on = 0 i avdd_off 15 a 6 over all current consump - tion in application mode active mode 1 ) i active 2.0 2.25 ma 7 over all current consump - tion in application mode idle mode (i idle = i off + i avdd_off ) i idle 16 50 a 8 state change from standby to run mode tstand - by2run 3 1/fsys 9 state change from off to run mode toff2r un 5 1/fsys table 4.1.1 supply: parameters ____________ 1 ) in application mode the current consumption is calculated from the duty cycle of the digital operating cur - rent and the analogue operating current. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 6 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.2 reset generation no. parameter condition symbol min. typ. max. unit 1 power on reset level reference is d vdd v por 2.25 v 2 brown out high-to-low threshold level reference is d vdd v bohl 1.95 v 3 brown out reset hysteresis v bohyst 100 200 300 mv 4 minimum supply voltage for power on reset and brown out circuit ? vdd min 0.9 v 5 nrst-pin low-to-high threshold level nrst lh 0.80 v ddi 6 nrst-pin high-to-low threshold level nrst h l 0.25 v ddi 7 pull up current nrst-pin v nrst = v ddi i nrstpu 20 a 8 min. pulse width for a valid reset at pin nrst (denoun - cing) d vdd > d vdd min t debnrst 200 - ns 9 delay watchdog start ? reset ? t wdog timer value 1/fsys table 4.2.1 reset generation ? : will not be tested in production test 4.3 internal clock generation 4.3.1 reference clocks no. parameter condition symbol min. typ. max. unit 1 wakeup clock frequency within recom - mended operating conditions f wk 115.2 128.0 140.8 khz 2 master clock within recom - mended operating conditions fsys 7.2 8.0 8.8 mhz table 4.3.1.1 reference clocks this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 7 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.4 module description 4.4.1 i2c interface no. parameter condition symbol min. typ. max. unit 1 sda/scl: input voltage low 1 ) v il -0.3 0.3 v ddi v 2 sda/scl: input voltage high 1 ) v ih 0.7 v ddi v ddi + 0.3 v 3 sda/scl: hysteresis of schmitt trigger inputs ? v ddi > 2.0 v v hys 0.05 v ddi - v 4 v ddi < 2.0 v v hys 0.1 v ddi - v 5 sda/scl: output voltage low, (open drain) i = 3 ma v ddi > 2.0 v v ol 0.4 v 6 i = 3 ma v ddii < 2.0 v v ol 0.2 v ddi v 7 sda/scl: input current 0 < v in < v ddi i i -10 10 a 8 sda/scl: capacitance ? c i - 10 pf 9 scl clock frequency f scl 0 400 khz 10 hold time (repeated) start condition ? t hd.:sta 600 - ns 11 low period of scl clock t low 1300 - ns 12 high period of scl clock t high 600 - ns 13 set-up time for repeated start condition ? t su.:sta 600 - ns 14 data hold time ? t hd.dat 0 900 ns 15 data set-up time ? t su:dat 100 - ns 16 rise time of sda and scl sig - nals with a bus capacitance (c b ) from 10 pf to 400 pf ? t r 20 + 0.1 c b 300 ns 17 fall time of sda and scl sig - nals with a bus capacitance (c b ) from 10 pf to 400 pf ? t f 20 + 0.1 c b 300 ns 18 sda/scl: output fall time from v ih to v il with a bus capa - citance (c b ) from 10 pf to 400 pf ? t of 20 + 0.1 c b 250 ns 19 set-up time for stop condi - tion ? t su:sto 600 - ns 20 bus free time between stop and start ? t buf 1300 - ns 21 pulse width of spikes which must be suppressed by the asic-internal input filter t sp 0 50 ns table 4.4.1.1 i2c interface ? : will not be tested in production test this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 8 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.4.2 spi module no. parameter condition symbol min. typ. max. unit 1 sck pulse low width / pulse high width transfer tck 4 1/fsys 2 first sck after falling csb start of transfer tcs1 2 1/fsys 3 last sck before rising csb end of transfer tcs2 2 1/fsys 4 set-up time tsetup 1 1/fsys 5 hold time thold 1 1/fsys 6 data out after shift tso 3 1/fsys 7 csb high time tcsh 2 1/fsys 8 data out change from z to driven data start of transfer tz1 1 1/fsys 9 data out change from driven data to z end of transfer tz2 1 1/fsys figure 4.4.2-1 sp i bus timing diagram this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 9 / 67 qm-no.: 25ds0014e.00 2nd bit si csb last bit 1st bit so tcs1 tcs2 tcsh tsetup tz2 thold tz1 z 2nd bit last bit z sck sample edge sck shift edge tck tck tck tck tso 1st bit
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.4.3 gpio module no. parameter condition symbol min. typ. max. unit 1 low-to-high threshold level gpio lh 0.80 v ddi 2 high-to-low threshold level gpio hl 0.25 v ddi 3 pull down resistor v in > 0.75 v ddi r gpiopd 43 61 119 k 4 output voltage low gpioiol = 2 ma vddi = 1.8 v gpiovol 0.4 v 5 output voltage high gpioioh = 2 ma vddi = 1.8 v gpi - ovoh 1.4 v 6 low level output current gpiovol=0.4v gpioiol 3.5 5.7 7 ma 7 high level output current gpiovoh=2.4v gpioioh -12.8 -8 -3.9 ma 8 tri-state input/output leak - age current vout=vddi or 0 v gpioilc -1 1 ua table 4.4.3.1 io interface ? : will not be tested in production test 4.4.4 halios interface 4.4.4.1 current generation for led modulators no. parameter condition symbol min. typ. max. unit 1 dac resolution n 10 bit 2 integral non linearity (inl) ei 2 lsb 3 differential non linearity (dnl) ed 2 lsb 4 dac output voltage at full scale v max 1.22 v table 4.4.4.1.1 transmitting path: 10 bit dac this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 10 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.4.4.2 led driver 1 -4 no. parameter condition symbol min. typ. max. unit 1 regulated proportion of led current @ dac = 0 dac = 0 i r_mins 5 % of i r_maxs 1 ) ma 2 max. regulated proportion of led current (range) range = 31 dac = 1023 i r_maxs 10.0 ma 3 step size for regulated current-range configuration i r_ steps 312.5 a 4 resolution current-range configuration n rs 5 bit 5 max. fixed proportion of led current (offset) offset = 31 i o_maxs 10.0 ma 6 step size for fixed offset- current configuration i o_steps 312.5 a 7 resolution offset-current configuration n os 5 bit 8 dc-bias current i bias s 200 a table 4.4.4.2.1 transmitting path: current sources led1-4 ________ 1 ) i r_maxs is the maximum current selected with parameter range (parameter range described in chapter fehler: referenz nicht gefunden on page fehler: referenz nicht gefunden ). 4.4.4.3 led driver c no. parameter condition symbol min. typ. max. unit 1 regulated proportion of led current @ dac = 0 dac = 0 i r_minc 5 % of i r_maxs 1 ) ma 2 max. regulated proportion of led current (range) range = 31 dac = 1023 i r_maxc 4.0 ma 3 step size for regulated current-range configuration i r_ stepc 125.0 a 4 resolution current-range configuration n rc 5 bit 5 max. fixed proportion of led current (offset) offset = 127 i o_maxc 5.0 ma 6 step size for fixed offset- current configuration i o_stepc 40.0 a 7 resolution offset-current configuration n oc 7 bit 8 dc-bias current i bias c 100 a table 4.4.4.3.1 transmitting path: current source ledc ________ 1 ) i rangemaxsx is the maximum current selected with parameter range (parameter range described in chapter fehler: referenz nicht gefunden on page fehler: referenz nicht gefunden ). this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 11 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 4.4.4.4 receiver no. parameter condition symbol min. typ. max. unit 1 transimpedance at ampli - fier input (ca) rf 70 100 130 k w 2 dc photo-current compens - ation i dc 1000 m a 3 voltage at transimpedance amplifier input v ka 1.25 v 4 corner frequency high pass filter f g 22 khz 5 gain amplifier g 0 30 db 6 total gain g tot 130 db w 7 center frequency f c 125 khz 8 resolution demodulator output n demod - 1 - bit 9 capacitance of photo diode at input ca c diode 70 pf 10 internal reference voltage v ref 1.22 v 11 internal reference current i bias 10 m a table 4.4.4.4.1 receiver 5 functional description 5.1 introduction the general architecture of the 3d-optical input device is shown in the system block diagram. the cpu is connected to the memory (flash and sram) and the peripheral modules via the internal sys - tem bus. the system bus provides a 16 bit address space and allows 8 and 16 bit data transfers. the memory contains the program code and the data. memory and registers are mapped to the global memory map and can be accessed through all memory related operation provided by the cpus instruction set. the memory of the asic consists of a 16kx16 (32kbyte) flash cell and a 1.5kx16 (3kbyte) sram cell. the interrupt controller collects requests from all interrupt sources and provides an interrupt signal to the cpu. interrupt sources can be masked within the interrupt controller. interrupts are generated by the mod - ules and hold until they are cleared within the module. see module description for clearing procedures. the spi can be configured either as a master or a slave. transfer length is eight bit and can be extended by a multiple of eight bit. data fifos are provided for transmit and receive tasks. the timer module contains a 32 bit timer module as well as a watchdog timer. additionally a second timer module operating on wakeup clock is implemented that remains active even in off mode, so it can be used for a periodical wake up from off mode for applications that require a low current consumption. 6 io port pins can either be configured as general purpose io`s or can be configured as ports for the spi or jtag module. additionally two ports are reserved for the i 2 c slave interface. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 12 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 a more detailed diagram of the clock / reset generation block (crg) is shown in the following sections. the clock and reset generator module provides the system clock and the global reset signal. a power-on-re - set, brown out detect and a power watch are implemented. as external reset source a reset input will be con - sidered. the system clock is generated by two on-chip oscillators. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 13 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 5.2 supply voltages 5.2.1 block diagram figure 5.2.1-1 block diagram of power supply 5.2.2 functional description three separate power supplies are needed to operate the asic . the core voltage supplying all digital blocks, the analog parts needed for the oscillator and supply observation as well as the preamplifiers of the output pads and the io supply which powers the post drivers of the gpio pads. the third supply is used for the halios measurement analog part. in the figure above the different power supply regions are depicted. 5.2.3 power up sequence considerations during power-up the power-on-reset configures all pads as inputs consequently disabling the output drivers. the io supply is watched after power up if the core supply is in the specified range and causes a reset if it leaves the allowed region. the core supply is watched via a brown out circuit. the pads will remain input pads as long as the software does not reconfigure them. according the following diagram it must be guaranteed that advv / dvvc is not switched on before vddio. nrst can be switched on if the vddio and avdd/dvvc are stabilized on its potential. a >= 0ms b > 5ms (recommended) to avoid floating gates, a < 100s is recommended. fig. 5.2.3-1 : power up sequence: a >= 0 ms; b > 5 ms this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 14 / 67 qm-no.: 25ds0014e.00 el16 core flash dvdd dvss peripherie gpio interface avdd avss analog crg vddi vssi ram ledvss led1-4
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 5.2.4 power down sequence considerations during power down the chip will enter the reset state as soon as the core or io supply leaves the specified region bringing all pads into input configuration again. note! it has to be assured that vddio C vddc > -0.3v at any time during power up and power down. 5.3 brown out detection 5.3.1 timing diagram figure 5.3.1-1 brown-out timing diagram 5.3.2 functional description the brown out detection of the chip will cause a reset whenever the core or io power supply falls below the specified region. an over-voltage protection is not implemented. the circuit will not be operational when the core supply is below vddmin. in these cases the power-on-reset will take care of proper reset generation. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 15 / 67 qm-no.: 25ds0014e.00 vddmin dvdd / vddi dvdd/vddi_ok t vdd undefined behavior vbohl brown-out v b o h y s t black-out v b o h y s t
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 5.4 reset generation 5.4.1 reset generation (resgen) the asic is equipped with a reset input pin which can be used to reset the chip. any low pulse longer than tdebnrst on the external reset line will be sensed and causes an asic reset. the asic contains different dynamic and static reset sources. the static sources trigger the master reset as long as the cause for the reset persists. the dynamic sources trigger the reset for a defined minimum reset time. after that time has expired the system reset is released. in case the dynamic source is still signaling a reset the reset is re-triggered. static reset sources: ? a power up sequence of the core voltage (power on reset) ? brown out of the core voltage dynamic reset sources: ? sram parity error ? cpu register parity error ? watchdog time out figure 5.4.1-1 timing of the external reset signal this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 16 / 67 qm-no.: 25ds0014e.00 nrst_pad in nrst_deb t tdeb_nrst filtered by debouncer
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 5.4.2 power-on-reset 5.4.2.1 timing diagram figure 5.4.2.1-1 power-on-reset timing diagram 5.4.2.2 functional description the power on reset is designed to cause a reset during the power on cycle of the chip. the reset will be deactivated when the supply crosses vpor. after the power up sequence the power on reset block will only cause a new reset if the power supply voltage drops below vddmin and the rise and fall times of the supply are below the specified values. 5.5 system failsafe features failsafe feature asserts interrupt asserts reset flash write detection x ram byte parity x uninitialized ram word / byte read detection x cpu register parity x cpu undefined opcode detection x cpu misaligned word access detection x opcode execution memory protection x stack overflow detection x invalid module register access detection x watchdog time out x watchdog window protection x brownout detection (supply voltage monitoring) x table 5.5.1 : fail-safe features this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 17 / 67 qm-no.: 25ds0014e.00 vpor dvdd / vddi npor t vdd end of power-on-reset brown-out is not detected vddmin
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 5.6 halios interface 5.6.1 block diagram figure 5.6.1-1 block diagram 5.6.2 features the asic contains a configurable halios interface. it is possible to drive up to four sending leds and one compensation led. the halios measurement loop is closed by a 10 bit dac which regulates the output current for the sending/compensation led. the dac is controlled by a counter that sets the dac dependent on the received signal amplitudes up or down. to follow fast signal changes the counter can be increased or decreased by 1, 2, 4 or 8 steps, this is called the step size that is set due to the number of up/down-counts in the same direction. to start a new measurement the interface is configured with the counter-value and the step size (generally the values from the last measurement), the led configuration and the current configura - tion for the led driver. the measurement regulates the dac and performs 25 counter steps to follow the actual reflection conditions of the sensor. after one measurement the interface returns the counter-value, the mean-value (it is calculated from the last 16 counter-steps during one measurement) and the step size from the last integrator cycle. after the automated measurement cycle is finished an interrupt appears if the inter - rupt is enabled. the interrupt is used to wake the system from standby mode.. 5.6.3 halios module registers address offset reset value register name size 0x00 0x0000 start value counter 16 0x02 0x0000 measurement configuration 16 0x04 0x0000 current configuration phase a 16 0x06 0x0000 current configuration phase b 16 this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 18 / 67 qm-no.: 25ds0014e.00 m u x demod. ca led1 led2 led3 led4 ledc rst clocks register dac current control dac dac dac dac 10 bit counter hp clk adr din dout 2 1 1 10 5 5 5 5 12 offset offset range range config analog digital dac 5 offset ledc an
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 address offset reset value register name size 0x08 0x00 current configuration compensator offset 8 0x0a 0x0000 measurement result: counter value 16 0x0c 0x0000 measurement result: mean value 16 0x0e 0x00 interrupt 8 table 5.6.3.1 : module registers register start value counter (0x00) msb lsb content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:12 : stz: startup step size for one step of the integrator (range: "0001", "0010", "0100" or "1000") 10 : 0 - normal settling time of optical gyrator 1 - decrease settling time of optical gyrator 9:0 : strtcnt: startup counter - value from the integrator (range: 0 ... 1023) table 5.6.3.2 : start value counter this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 19 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register measurement configuration (0x02) msb lsb content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/ w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15 : halmeas: starts a new measurement phase, switching from '0' to '1' starts measure - ment. after measurement the bit resets itself. 14 : accon: en/disables the acceleration of the integrator ('0' = disabled, '1' = enabled) 13 : deactivation of an input to reduce current consumption in the case that only the ca input is used ('0' = active, '1' = deactivated) 12 : aon: control of analogue part ('0' = off, '1' = on) 11 : fixb: sets the leds activated in phase b to fixed sending current ('0' = variable, '1' = fixed) 10 : fixa: sets the leds activated in phase a to fixed sending current ('0' = variable, '1' = fixed) 9 : led c a: decides if led is active for the measurement ('0' = off, '1' = on) note: bits 9 down to 0 will be reset after measurement 8 : led c b: decides if led is active for the measurement ('0' = off, '1' = on) 7 : led 4 a: decides if led is active for the measurement ('0' = off, '1' = on) note: not available in version 1 and version 2 6 : led 4 b: decides if led is active for the measurement ('0' = off, '1' = on) note: not available in version 1 and version 2 5 : led 3 a: decides if led is active for the measurement ('0' = off, '1' = on) note: not available in version 1 and version 2 4 : led 3 b: decides if led is active for the measurement ('0' = off, '1' = on) note: not available in version 1 and version 2 3 : led 2 a: decides if led is active for the measurement ('0' = off, '1' = on) 2 : led 2 b: decides if led is active for the measurement ('0' = off, '1' = on) 1 : led 1 a: decides if led is active for the measurement ('0' = off, '1' = on) 0 : led 1 b: decides if led is active for the measurement ('0' = off, '1' = on) table 5.6.3.3 : measurement configuration this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 20 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register current configuration phase a (0x04) msb lsb content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 9:5 : off: offset phase a 4:0 : rng: range phase a table 5.6.3.4 : current configuration phase a register current configuration phase b (0x06) msb lsb content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 9:5 : off: offset phase b 4:0 : rng: range phase b table 5.6.3.5 : current configuration phase b transmitting current led1-4: i n the regulated mode (fixa/b = '0') the total current is i total = i offset i regulate 1023 ? i range i bias s , with i regulate = 0 ... 1023 (10 bit dac) i offset = offset * i o_steps i range = range * i r_steps in constant mode (fixa = '1' or fixb = '1'): i total = i offset i range 2 i bias s where i bias s is a small current which always keeps the leds turned on to maximise speed and minimise parasitic effects. register current configuration compensator offset (0x08) msb lsb content 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w external access r r r r r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w bit description 11:8 : dc_offset current ledc (4 bit) 6:0 : offset compensation ledc table 5.6.3.6 : current configuration compensator offset the offset current for the terminal ledc is configureable with the seven bit value offset . this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 21 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 transmitting current ledc: t he total current in regulated mode (fixa/b = '0') for ledc is i total = i offset i regulate 1023 ? i range i bias c , with i regulate = 0 ... 1023 (10 bit dac) i offset = offset * i o_stepc i range = range * i r_stepc register measurement result: counter value (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:12 : stz: stepsize integrator 9:0 : count: integrator value from the measurement table 5.6.3.7 : measurement result: counter value register measurement result: mean value (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:12 : stz: stepsize integrator 11:0 : mean: mean value from the measurement table 5.6.3.8 : measurement result: mean value register interrupt (0x0e) bit 7 6 5 4 3 2 1 0 content - - - - - - 1 0 reset value 0 0 0 0 0 0 0 0 internal access r r r r r r r/w r/w external access r r r r r r r/w r/w bit description 1 : clhali: clear halios ? interrupt 0 - no influence 1 - clear halios ? interrupt 0 : halie: halios ? interrupt enable: 0 - interrupt disabled 1 - interrupt enabled table 5.6.3.9 : interrupt this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 22 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6 microcontroller el16 6.1 feature list the cpu incorporates features specifically designed for modern programming techniques such as calculated branching, table processing and the use of high-level languages such as c. the cpu can address the com - plete address range without paging. the cpu features include: ? risc architecture with 27 instructions and 7 addressing modes. ? orthogonal architecture with every instruction usable with every addressing mode ? full register access including program counter, status registers, and stack pointer ? 16 registers including pc, sp and status register ? non paged 16-bit address space ? word and byte addressing and instruction formats. ? single-cycle register operations. ? interrupt support ? standby and stop mode support ? bus wait support ? debugging support (jtag interface) ? failsafe architecture 6.2 debugging to access the debug structures of the el16 cpu a 4-wire standard jtag interface is used. the jtag inter - face can be accessed via the gpio pins 2 to 5 when the tmode pin is set to one. tmode pin set to zero resets all test and debug structures and the asic operates in normal mode (see fehler: referenz nicht gefunden fehler: referenz nicht gefunden for details). 6.3 cpu registers the el16 contains 16 registers (r0 to r15) including program counter, stack pointer and status register 6.3.1 program counter (pc) the 16-bit program counter (pc/r0) points to the next instruction to be executed. each instruction uses an even number of bytes (two, four, or six), and the pc is incremented accordingly. instruction accesses in the 64-kb address space are performed on word boundaries, and the pc is aligned to even addresses. the pc can be addressed with all instructions and addressing modes. 6.3.2 stack pointer (sp) the stack pointer (sp/r1) is used by the cpu to store the return addresses of subroutine calls and inter - rupts. it uses a pre-decrement, post-increment scheme. in addition, the sp can be used by software with all instructions and addressing modes. the sp is initialized into ram by the user, and is aligned to even addresses. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 23 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.3.3 status register (sr) the status register (sr/r2), used as a source or destination register, can be used in the register mode only addressed with word instructions. the remaining combinations of addressing modes are used to support the constant generator. register status register (sr/r2) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r r r r r r r r r r bit description bit 8 : v bit 5 : clk off bit 4 : cpu off bit3 : gie bit2 : n bit1 : z bit0 : c table 6.3.3.1 : status register v : overflow bit this bit is set when the result of an arithmetic operation overflows the signed-variable range. clkoff : stop flag cpu clock gated cpuoff : standby flag cpu halted gie : global interrupt enable n : negative bit this bit is set when the result of a byte or word operation is negative and cleared when the result is not negat - ive. word operation: n is set to the value of bit 15 of the result byte operation: n is set to the value of bit 7 of the result z : zero bit this bit is set when the result of a byte or word operation is 0 and cleared when the result is not 0. c : carry bit this bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred. 6.3.4 constant generation registers cg1 and cg2 six commonly-used constants are generated with the constant generator registers r2 and r3, without requir - ing an additional 16-bit word of program code. the constants are selected with the source-register address - ing modes (as), as described in the table below: register as value remarks r2 00 ----- register mode r2 01 (0) absolute address mode r2 10 00004h +4, bit processing this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 24 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register as value remarks r2 11 00008h +8, bit processing r3 00 00000h 0, byte processing r3 01 00001h +1 r3 10 00002h +2, bit processing r3 11 0ffffh -1, word processing table 6.3.4.1 : constant generation register cg1/cg2 table the constant generator advantages are: ? no special instructions required ? no additional code word for the six constants ? no code memory access required to retrieve the constant the assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand. registers r2 and r3, used in the constant mode, cannot be addressed explicitly; they act as source-only registers. 6.3.5 general-purpose register r4 - r15 the twelve registers, r4?r15, are general-purpose registers. all of these registers can be used as data registers, address pointers, or index values and can be accessed with byte or word instructions. 6.4 addressing modes seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions. the bit numbers in the table below describe the contents of the as(source) and ad (destination) mode bits. as/ad addressing mode syntax description 00/0 register mode rn register contents are operand 01/1 indexed mode x(rn) (rn + x) point to the operand. xis stored in the next word 01/1 symbolic mode addr (rn + x) point to the operand. xis stored in the next word. indexed mode x(pc) is used. 01/1 absolute mode &addr the word following the instruction con - tains the absolute address. x is stored in the next word. indexed mode x(sr) is used. 10/- indirect register mode @rn rn is used as a pointer to the operand. 11/- indirect auto increment @rn+ rn is used as a pointer to the operand. rn is incremented afterwards by 1 for .b instructions and by 2 for .w instructions. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 25 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 as/ad addressing mode syntax description 11/- immediate mode #n the word following the instruction con - tains the immediate constant n. indirect auto-increment mode @pc+ is used. table 6.4.1 : addressing modes table 6.5 el16 instruction set the complete el16 instruction set consists of 27 core instructions and 24 emulated instructions. the core instructions are instructions that have unique op-codes decoded by the cpu. the emulated instructions are instructions that make code easier to write and read, but do not have op-codes themselves, instead they are replaced automatically by the assembler with an equivalent core instruction. there is no code or performance penalty for using emulated instruction. there are three core-instruction formats: ? dual-operand ? single-operand ? jump all single-operand and dual-operand instructions can be byte or word instructions by using .b or .w exten - sions. byte instructions are used to access byte data or byte peripherals. word instructions are used to access word data or word peripherals. if no extension is used, the instruction is a word instruction. the source and destination of an instruction are defined by the following fields: abbr. description src the source operand defined by as and s-reg dst the destination operand defined by ad and d-reg as the addressing bits responsible for the addressing mode used for the source (src) s-reg the working register used for the source (src) ad the addressing bits responsible for the addressing mode used for the destination (dst) d-reg the working register used for the destination (dst) b/w byte or word operation: 0: word operation, 1: byte operation table 6.5.1 : source and destination of an instruction the following tables shows coding table of the 16 bit opcode: this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 26 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mnemonic 0 0 0 0 0 0 -- 0 0 0 1 0 0 0 0 0 0 ad/as d-reg/s-reg rrc 0 0 0 1 rrc.b 0 0 1 0 swp.b 0 0 1 1 --- 0 1 0 0 rra 0 1 0 1 rra.b 0 1 1 0 sxt 0 1 1 1 --- 1 0 0 0 push 1 0 0 1 push.b 1 0 1 0 call 1 0 1 1 --- 1 1 0 0 reti 1 1 0 1 --- 1 1 1 0 --- 1 1 1 1 --- 0 0 0 1 0 1 --- 1 0 --- 1 1 --- 0 0 1 0 0 0 10-bit pc offset jnz / jne 0 0 1 jz / jeq 0 1 0 jnc / jlo 0 1 1 jc / jhs 1 0 0 jn 1 0 1 jge 1 1 0 jl 1 1 1 jmp 0 1 0 0 s-reg ad b/w as d-reg mov 0 1 0 1 add 0 1 1 0 addc 0 1 1 1 subc 1 0 0 0 sub 1 0 0 1 cmp 1 0 1 0 dadd 1 0 1 1 bit 1 1 0 0 bic 1 1 0 1 bis 1 1 1 0 xor 1 1 1 1 and fig. 6.5-1 : coding of the 16 bit op-code this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 27 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 mnemonic parameters description v n z c adc(.b)** dst add c to destination dst + c -> dst * * * * add(.b) src, dst add source to destination src + dst -> dst * * * * addc(.b) src, dst add source to c and destination src + dst + c -> dst * * * * and(.b) src, dst and source and destination src and dst -> dst 0 * * * bic(.b) src, dst clear bits in destination not(src) and dst -> dst - - - - bis(.b) src, dst set bits in destination src or dst -> dst - - - - bit(.b) src, dst test bits in destination src and dst 0 * * * br dst branch to destination dst -> pc - - - - call dst call destination sp-2 -> sp, pc+2 -> @sp, dst -> pc - - - - clr (.b)** dst clear destination 0 0 -> dst - - - - clrc** --- clear c 0 0 -> c - - - 0 clrn** --- clear n 0 0 -> n - 0 - - clrz** --- clear z 0 0 -> z - - 0 - cmp (.b) src, dst compare source and destination dst - src * * * * dadc (.b)** dst add c decimally to destination dst + c -> dst 0 * * * dadd (.b) src, dst add source and c decimally to destination src + dst + c -> dst 0 * * * dec (.b)** dst decrement destination dst -1 -> dst * * * * decd (.b)** dst double decrement destination dst -2 -> dst * * * * dint** --- disable interrupts 0 0 -> gie - - - - eint** --- enable interrupts 1 1 -> gie - - - - inc (.b) dst increment destination dst +1 -> dst * * * * incd (.b)** dst double increment destination dst +2 -> dst * * * * inv (.b)** dst invert destination not(dst) -> dst * * * * jc / jhs label jump if c set / jump if higher or same if (condition) pc + 2 * offset -> pc - - - - jz / jeq label jump if z set / jump if equal if (condition) pc + 2 * offset -> pc - - - - jge label jump if greater or equal if (condition) pc + 2 * offset -> pc - - - - jl label jump if less if (condition) pc + 2 * offset -> pc - - - - jmp label jump pc + 2 * offset -> pc - - - - jn label jump if n set / jump if negative if (condition) pc + 2 * offset -> pc - - - - jnc /jlo label jump if c not set / jump if lower if (condition) pc + 2 * offset -> pc - - - - jnz / jne label jump if z not set / jump if equal if (condition) pc + 2 * offset -> pc - - - - mov (.b) src, dst move source to destination src -> dst - - - - nop --- no operation --- - - - - pop (.b)** dst pop item from stack to destination @sp+ -> dst - - - - push (.b) src push source onto stack sp -2 -> sp, src -> sp - - - - ret** --- return from subroutine @sp -> pc - - - - reti --- return from interrupt @sp -> sr, @sp+ -> pc * * * * rla (.b)** dst rotate left arithmetically dst * 2 -> dst * * * * rlc (.b)** dst rotate left through c dst * 2 -> dst, c -> lsb(dst) * * * * rra (.b) dst rotate right arithmetically dst / 2 -> dst 0 * * * rrc (.b) dst rotate right through c dst / 2 -> dst, c -> msb(dst) 0 * * * sbc (.b)** dst subtract not(c) from destination dst + not(0) + c -> dst * * * * setc** --- set c 1 -> c - - - 1 setn** --- set n 1 -> n - 1 - - setz** --- set z 1 -> z - - 1 - sub (.b) src, dst subtract source from destination dst + not(src) + 1 -> dst * * * * subc (.b)** src, dst subtract source and not(c) from destination dst + not(src) + c -> dst * * * * swpb dst swap bytes --- - - - - sxt dst extend sign --- 0 * * * tst (.b)** dst test destination dst + not (0) + 1 0 * * 1 xor(.b) src, dst exclusive or source and destination src xor dst -> dst * * * * fig. 6.5-2 : instruction set of el16 6.5.1 el16 instruction cycle counts this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 28 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 command type operation cycles cycles(dreg==pc) mov double sreg -> dreg sreg x dreg -> dreg 1 1 2 2 mov double sreg -> y(dreg) -> dreg sreg x y(dreg) -> ydreg 3 4 --- mov double @sreg -> dreg @sreg x dreg -> dreg 2 2 3 3 mov double @sreg -> y(dreg) -> dreg @sreg x y(dreg) -> ydreg 4 5 --- mov double @sreg+ -> dreg @sreg+ x dreg -> dreg 2 2 3 3 mov double @sreg+ -> y(dreg) -> dreg @sreg+ x y(dreg) -> ydreg 4 5 --- mov double xsreg+ -> dreg xsreg+ x dreg -> dreg 3 3 4 4 mov double xsreg+ -> y(dreg) -> dreg xsreg+ x y(dreg) -> ydreg 5 6 --- single single single single dreg @dreg @dreg+ y(dreg) --- --- --- --- 2 --- --- --- jump reti ircq --- --- --- 2 3 4 --- --- --- --- push push push push reg @reg @reg+ x(reg) 3 4 4 5 --- --- --- --- call call call call reg @reg @reg+ x(reg) 3 4 4 5 --- --- --- --- fig. 6.5.1-1 : el16 instruction cycle counts this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 29 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.6 memory description 6.6.1 memory map figure 6.6.1-1 : memory map this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 30 / 67 qm-no.: 25ds0014e.00 sram 1.5k x 16 (3 kbyte) flash 16k x 16 (32 kbyte) gpio 0x0000 0xffff modules 0x1000 0x0400 0x0200 unused spi timer 0 (wdog) unused multiplier irq control i2c flash control analog control memory protection halios measurement reserved 0x0200 0x0000 timer 1 unused unused 0x8000
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.6.2 base address table base address size module name 0x8000 0x7fff flash 0x1000 0x7000 reserved 0x0400 0x0c00 sram 0x0200 0x0200 reserved 0x01e0 0x0020 reserved 0x01c0 0x0020 memory protection module 0x01a0 0x0020 analogue control module 0x0180 0x0020 flash control module 0x0160 0x0020 i2c module 0x0140 0x0020 interrupt control module 0x0120 0x0020 multiplier module 0x0100 0x0020 reserved 0x00e0 0x0020 timer module 1 0x00c0 0x0020 timer module 0 (watchdog) 0x00a0 0x0020 spi module 0x0080 0x0020 reserved 0x0060 0x0020 gpio module 0x0040 0x0020 halios measurement module 0x0020 0x0020 reserved 0x0000 0x0020 reserved table 6.6.2.1 : base address table this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 31 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.6.3 flash ? main block size: 16k x 16bit (32 kbyte) ? info block size: 64 x 16bit (128 byte) ? for flash test mode details see flash control and test mode description 6.6.4 sram ? size: 1.5k x 16bit (3kbyte) ? byte write enable support ? each byte is extended by a parity bit 6.7 memory protection module ? opcode execute area configuration (granularity: 1kbyte, 64 areas) ? stack area configuration (granularity: 256byte, 12 areas) ? invalid module register address handling 6.7.1 memory protection module registers address offset reset value register name size 0x00 0x0000 opcode execute enable 0 16 0x02 0x0000 unused 16 0x04 0xffff opcode execute enable 2 16 0x06 0xffff opcode execute enable 3 16 0x08 0x0000 execute address value 16 0x0a 0x0fff stack enable 16 0x0c 0x0000 invalid address value 16 0x0e - interrupt clear 16 table 6.7.1.1 : memory protection module registers register op-code execute enable 0 (0x00) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15 :4 unused enable 0 - execution of opcode denied 1 - execution of opcode allowed area size: 1 kbyte bit 0 - area 0x0000 to 0x03fe bit 1 - area 0x0400 to 0x07fe bit 2 - area 0x0800 to 0x0bfe bit 3 - area 0x0c00 to 0x0ffe this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 32 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 table 6.7.1.2 : op-code execute enable 0 register op-code execute enable 1 (0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description enable 0 - execution of opcode denied 1 - execution of opcode allowed area size: 1 kbyte bit 0 - area 0x4000 to 0x43fe bit 1 - area 0x4400 to 0x47fe .... bit 15 - area 0x7000 to 0x7ffe table 6.7.1.3 : op-code execute enable 0 register op-code execute enable 2 (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description enable 0 - execution of opcode denied 1 - execution of opcode allowed area size: 1kbyte bit 0 - area 0x8000 to 0x83fe bit 1 - area 0x8400 to 0x87fe .... bit 15 - area 0xb000 to 0xbffe table 6.7.1.4 : op-code execute enable 2 register op-code execute enable 3 (0x06) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description enable 0 - execution of opcode denied 1 - execution of opcode allowed area size: 1kbyte bit 0 - area 0xc000 to 0xc3fe bit 1 - area 0xc400 to 0xc7fe .... bit 15 - area 0xf000 to 0xfffe table 6.7.1.5 : op-code execute enable 3 this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 33 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register execute address value (0x08) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:0 : address of last denied opcode access table 1 : failure address value register stack enable (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 internal access r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description enable 0 - use as stack denied 1 - use as stack allowed area size: 256byte bit 0 - area 0x0400 to 0x04fe bit 1 - area 0x0500 to 0x05fe .... bit 11 - area 0x0f00 to 0x0ffe table 2 : stack enable register invalid address value (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:0 : address of last invalid module register access table 3 : invalid address value this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 34 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register interrupt clear (0x0e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - w w w w w external access - - - - - - - - - - - w w w w w bit description 4 : undefined op-code irq clear (address of undefined op-code can be obtained by look - ing to the return address stored in stack minus - 2) 0 - no influence 1 - clear interrupt 3 : misaligned 16 bit access irq clear 0 - no influence 1 - clear interrupt 2 : invalid address irq clear 0 - no influence 1 - clear interrupt 1 : stack protection irq clear 0 - no influence 1 - clear interrupt 0 : execute protection irq clear 0 - no influence 1 - clear interrupt table 4 : interrupt clear this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 35 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.8 analogue control module ? controls clock and reset generator (crg) 6.8.1 analogue control module registers address offset reset value register name size 0x00 0x0010 wakeup timer config 16 0x02 0x0000 mclk trim value 16 0x04 0x0000 wkclk trim value 16 0x10 - reset source status 16 0x12 - reset source status clear 16 0x14 - wakeup timer interrupt status 16 0x16 - wakeup timer interrupt clear 16 table 6.8.1.1 : analog control module registers register wake-up timer config (0x00) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r r r r/w r/w r/w r/w r/w bit description 15:8 : password must be written as 0xa5, will always be read as 0x96 4 : enable timer 0 - timer off 1 - timer on 3:0 : timer value: timer period = 2 ms * [timer value + 1], with timer value 0...15 table 6.8.1.2 : wake-up timer config this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 36 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register mclk trim value (0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:4 : unused 3:0: trim value for master clock oscillator: 0111: lowest frequency 0000: centre frequency 1000: highest frequency table 6.8.1.3 : mclk trim value register wklk trim value (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:4 : unused 3:0: trim value for wakeup clock oscillator: 0111: lowest frequency 0000: centre frequency 1000: highest frequency table 6.8.1.4 : wk clk trim value register reset source status (0x10) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15 : level of incoming external reset signal (nrst) 8 : trap -> masked interrupt event occurred (interrupt number 0 and 1) 7 : ram parity error 6 : flash uncorrectable bit error 5 : cpu register parity error 4 : watchdog reset 1 : external reset 0 : power on reset / supply observe / trim register ecc error table 6.8.1.5 : reset source status register reset source status clear (0x12) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - - - w external access - - - - - - - - - - - - - - - w this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 37 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit description 0 : clears all reset status bits 0 - no influence 1 - clears all reset status bits table 6.8.1.6 : reset source status clear register wake-up timer interrupt status (0x14) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 0 : wake-up timer interrupt status 0 - no interrupt 1 - interrupt was asserted table 6.8.1.7 : wake-up timer interrupt status register wake-up timer interrupt clear (0x16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - - - w external access - - - - - - - - - - - - - - - w bit description 0 : timer irq clear 0 - no influence 1 - clear interrupt table 6.8.1.8 : wake-up timer interrupt clear 6.9 flash control module ? flash area protection (area size: 2k words) ? main and info block read, program, page erase and mass erase support ? software adaptable program and erase timing this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 38 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.9.1 flash control module registers address offset reset value register name size 0x00 0x9600 area protection (areas 7 - 0) 16 0x02 0x9600 area protection (info block) 16 0x04 0x9600 mode 16 0x06 - status 16 0x08 - irq clear 16 0x0a 0 wait cycle register 16 0x0c 0 bit error corrected address 16 0x10 6 tnvs / tnvh 16 0x12 120 tnvh1 16 0x14 12 tpgs 16 0x16 1 tpgh 16 0x18 2 trcv 16 0x1a 30 tprog 16 0x1c 6 terase 16 0x1e 60 tme 16 table 6.9.1.1 : flash control module registers register area protection (areas 0 - 7) (0x00) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:8 : password must be written as 0xa5 will always be read as 0x96 7:0 : writeable 0 - area protected 1 - area writeable areas 0 - 7 are flash main block areas (8 * 2k words) table 6.9.1.2 : area protection (areas 0 - 7) register area protection (info_block) (0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 39 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit description 15:8 : password must be written as 0xa5 will always be read as 0x96 7 writeable 0 - area protected 1 - area writeable 6:0 : reserved table 6.9.1.3 : area protection (info block) register mode (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:8 : password must be written as 0xa5 will always be read as 0x96 7:0 : mode 0x01 - main block read 0x02 - info block read 0x04 - main block program 0x08 - info block program 0x10 - erase main block page 0x20 - erase info block 0x40 - mass erase main block 0x80 - mass erase main and info block every over written mode value results in "main block read" mode table 6.9.1.4 : mode register status (0x06) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 2 : write error unexpected flash write access this bit is cleared by write error irq clear 1 : row programming incomplete current number of programmed row words != word config (see below) 0 : busy 0 - ready 1 - busy (program or erase is still in progress) table 1 : status this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 40 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register irq clear (0x08) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - - - w external access - - - - - - - - - - - - - - - w bit description 0 : write error irq clear 0 - no influence 1 - clear interrupt table 2 : irq clear register wait cycle register (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:8 : password must be written as 0xa5 will always be read as 0x96 wait cycles per flash read access table 3 : wait cycles register register bit error corrected address (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:0 : address of last correctable flash bit error table 4 : bit error corrected address register tnvs/tnvh (0x010) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 5 : tnvs/tnvh register tnvh1 (0x012) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 41 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 6 : tnvh1 register tpgs (0x014) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 7 : tpgs register tpgh (0x016) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 8 : tpgh register trcv (0x018) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 9 : trcv this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 42 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register tprog (0x01a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 8 system clock cycles (1us, when fsys is 8 mhz) 2 - 2*8 system clock cycles ... this register can only be written, when mode is not "main block read" table 10 : tprog 6.9.2 terase / tme register terase (0x01c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 32000 system clock cycles (4096 us, when fsys is 8 mhz) 2 - 2*32000 system clock cycles ... this register can only be written, when mode is not "main block read" table 6.9.2.1 : terase register tme (0x01e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description time 0 or 1 - 32000 system clock cycles (4096 us, when fsys is 8 mhz) 2 - 2*32000 system clock cycles ... this register can only be written, when mode is not "main block read" table 6.9.2.2 : tme this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 43 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.10 i2c interface 6.10.1 i2c block diagram figure 6.10.1-1 block diagram 6.10.2 i2c function the i2c slave interface operates in 7 bit addressing mode with a maximum frequency of 400 khz (fast mode). to synchronize the asic to different operation voltages of the i2c bus the interface has a separate supply voltage input at pin v ddi which is responsible for all interface pins. for more details of the addressing modes please refer to the i2c C bus specification version 2.1 from philips. 6.10.3 i2c bus timing diagram figure 6.10.3-1 i2c bus timing diagram this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 44 / 67 qm-no.: 25ds0014e.00 stop detection start detection receive write byte control high water range receive fifo 8 send read byte send fifo 8 sda scl sdaout sdain sclout sclin high water interrupt high water level receive data low water range low water interrupt low water level send data set/clear wakeup enable wakeup 4 3 2 1 bit count slave address clear receive fifo range range clear send fifo 4 3 2 1 0 0 0 0 1 1 1 1 0 0 1 t hd:sta t low t high t su:dat t hd:dat t su:sta t sp t su:sto t buf sda scl t f t r
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.10.4 i2c module registers address offset reset value register name size 0x00 0x00 receive data fifo register 8 0x02 0x00 send data fifo register 8 0x04 0x0040 control register 16 0x06 0x0000 status register 16 table 6.10.4.1 : i2c module registers 6.10.5 data fifo registers receive data fifo registers the data received from the master is stored in the receive fifo registers and has a depth of 4. the current fill level can be read in the status register. if the fifo is completely filled up and another byte should be received the interface will force the master into a wait state until the application software reads one byte from the fifo. register receive data fifo register (0x00) bit 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 internal access r r r r r r r r external access r r r r r r r r bit description 7:0 : receive data (see data fifo registers for details) table 6.10.5.1 : receive data fifo register send registers: the master reads data that is stored in the send fifo registers. this fifo buffer has a depth of 4 registers. the current fill level can be read in the status register. if the fifo is empty and a byte is requested by the master the interface will force the master into a wait state until the application software writes one byte to the fifo. register send data fifo register (0x02) bit 7 6 5 4 3 2 1 0 reset value - - - - - - - - internal access w w w w w w w w external access w w w w w w w w bit description 7:0 : send data (see data fifo registers for details) table 6.10.5.2 : send data fifo register 6.10.6 control register register control register (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 internal access r r r/w r/w r/w r/w r/w r/w r r/w r/w r/w r r/w r/w r/w external access r r r/w r/w r/w r/w r/w r/w r r/w r/w r/w r r/w r/w r/w this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 45 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit description 15:14 reserved 13 : clear contents of send fifo registers 0 - read 1 - write 12 : clear contents of receive fifo registers 0 - read 1 - write 11 : clear wake-up mode enable bit (see description below) 0 - read 1 - write 10 : set wake-up mode enable bit (see description below) 0 - read 1 - write 9:8 : slave address "00" - $58 (reset value) "01" - $59 "10" - $5a "11" - $5b 7: reserved 6:4 : high water range for receive fifo (range 0....4) 3: reserved 2:0 : low water range for send fifo (range 0....4) table 6.10.6.1 configuration register: i2c control register 6.10.7 status register register status register (0x06) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:9 reserved 8 : wake-up mode enable bit 0 - wake-up mode disabled 1 - wake-up mode enabled 7: reserved 6:4 : fill level of receive fifo 3: reserved 2:0 : fill level of send fifo table 6.10.7.1 configuration register: i2c status register 6.10.8 interrupt handling i2c receive command (see 6.11.2 list of all interrupts ) this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 46 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 command word pending in receive fifo, this means the next byte read from the receive fifo is the first received byte after the slave has been addressed. depending on the application software this byte could be interpreted as a command. the interrupt flag is set back by reading a byte from the receive fifo. t he master will force the interface into a wait state until the application software reads one byte from the fifo. i2c send request (see 6.11.2 list of all interrupts ) this flag signalises that the master is requesting a byte but the send fifo is empty. the interrupt flag is set back by writing a byte to the send fifo. t he master will force the interface into a wait state until the application software writes one byte to the fifo. if this interrupt is not used for the communication protocol a default routine has to be implemented to clear the interrupt in case of unintentional appearance of this interrupt (the interrupt can occur under different cir - cumstances when the slave address is enclosed in a data byte). c-code example for default routine: i2c_txdata = 0xff; // fill send data fifo register (see above) // with one byte of data to clear the interrupt i2c_ctrl |= i2c_clrtxfifo; // clear contents of send fifo registers to // remove previous written 0xff (control reg.) i2c send fifo low water (see 6.11.2 list of all interrupts ) in case the low water mark (defined in control register) is reached or is exceeded the send fifo low water flag becomes active. the flag is set back by filling to the send fifo. i2c receive fifo high water (see 6.11.2 list of all interrupts ) if the high water mark (defined in control register) is reached or is exceeded the receive fifo high water flag becomes active. the flag is set back by reading from the receive fifo. 6.10.9 i2c wake-up detection the i2c interface can be used to wake up the asic from any system state. in system state off the interface has to be configured to wake the cpu. therefore the 'wakeup mode enable bit' has to be set (defined in con - trol register) before setting the asic to off-mode. it is only possible to set the 'wakeup mode enable bit' if the i2c master has closed the communication on the bus, so the application software has to poll the bit 'wakeup mode enable' (defined in status register) after it was set to make sure the bus is in idle state and the asic can be set to off-mode. after a new addressing of the slave on the bus the system will wake up from off-mode and the i2c wakeup event interrupt is active as long as the 'wakeup mode enable bit' is set back to zero (defined in control register). while the wake-up process the interface will force the master into a wait state by holding the scl line low. the application software has to clear the 'wakeup mode enable bit' (defined in control register) to release the scl line in order to continue the communication. 6.11 interrupt control module 6.11.1 interrupt control module structure ? interrupt pending bit flipflops (request hold elements) are located inside asserting modules ? interrupt vector support for more simple and faster interrupt entry ? nested interrupt support ? main interrupt enable mie for easy cli() and sei() implementation ? n is the number of interrupt vectors this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 47 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 figure 6.11.1-1 : interrupt control circuit this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 48 / 67 qm-no.: 25ds0014e.00 and module and gpio interrupt sources interrupt mask interrupt status masked interrupt status vector logic interrupt vector or interrupt to cpu n n 1 n n n mie
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.11.2 list of all interrupts vector number interrupt source priority 0 undefined opcode highest 1 misaligned word access 2 opcode execute protection error 3 stack protection error 4 invalid module register address access 5 flash write error 6 halios measurement ready 7 timer0 window error (watchdog) 8 timer1 window error 9 timer1 event 10 i2c receive command 11 i2c send request 12 i2c send fifo low water 13 i2c receive fifo high water 14 spi timeout 15 spi fifo error 16 spi receive high water 17 spi send low water 18 gpio rising 19 gpio falling 20 i2c wakeup event 21 wakeup timer wakeup event 22 reserved 23 reserved 24 reserved 25 reserved 26 reserved 27 reserved 28 reserved 29 reserved 30 reserved 31 reserved lowest table 6.11.2.1 : list of all interrupts this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 49 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.11.3 interrupt control module registers address offset reset value register name size 0x00 0x0000 interrupt mask 32 0x04 - interrupt status 32 0x08 - masked interrupt status 32 0x10 - interrupt vector number 16 0x12 0x0000 interrupt routine address 16 0x14 0x0020 maximum interrupt level 16 0x16 0x0001 main interrupt enable 16 table 6.11.3.1 : interrupt control module registers 6.11.4 interrupt mask register interrupt mask (0x00) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w external access r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w bit description 31:0 : mask (see list of all interrupts for details) 0 - disable 1 - enabled table 6.11.4.1 : interrupt mask 6.11.5 interrupt status register interrupt status (0x04) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r bit description 31:0 : status (see list of all interrupts for details) 0 - not active 1 - active table 6.11.5.1 : interrupt status 6.11.6 masked interrupt status this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 50 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register masked interrupt status (0x08) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r bit description 31:0 : masked status (see list of all interrupts for details) 0 - not active 1 - active table 6.11.6.1 : masked interrupt status 6.11.7 interrupt vector number register interrupt vector number (0x10) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:0 : number (see list of all interrupts for details) vector number of pending interrupt with highest priority (smallest vector number) when no interrupt is pending, vector will be 0xffff reset value: 0x0000 table 6.11.7.1 : interrupt vector number 6.11.8 interrupt routine address register interrupt routine address (0x12) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : address address of the software interrupt routine (is directly provided to the cpu for use as inter - rupt routine entry address and must be initialized by software before enabling interrupts) table 6.11.8.1 : interrupt routine address this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 51 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.11.9 maximum interrupt level register maximum interrupt level (0x14) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 internal access r r r r r r r r r r r/w r/w r/w r/w r/w r/w external access r r r r r r r r r r r/w r/w r/w r/w r/w r/w bit description 5:0 : level needed for nested interrupt support software writes current vector number to this register, so only interrupts with higher priority (lower vector number) can nest. table 6.11.9.1 : maximum interrupt level 6.11.9.1 main interrupt enable register main interrupt enable (0x16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 internal access r r r r r r r r r r r r r r r r/w external access r r r r r r r r r r r r r r r r/w bit description mie main interrupt enable flag which can be used for easy implementation of cli() and sei() routines. note: cli() usually must check (save current enable status) and then clear interrupt enable flag atomic (non interruptable). el16 has no such operation, so gie flag cannot be used. gie should only be used for interrupt nesting. when mie is only used inside cli() and sei(), cli() must not save current status, because mie is always enabled on cli() entry. table 6.11.9.1.1 : main interrupt enable this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 52 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.12 m ultiplier module the hardware multiplier is a peripheral and is not part of the el16 cpu. this means, its activities do not inter - fere with the cpu activities. the multiplier registers are peripheral registers that are loaded and read with cpu instructions. the hardware multiplier supports: ? unsigned multiply ? signed multiply ? unsigned multiply accumulate ? signed multiply accumulate ? 16 x 16 bits, 16 x 8 bits, 8 x 16 bits, 8 x 8 bits ? cpu is halted until result is valid (1 clock cycle) the hardware multiplier supports unsigned multiply, signed multiply, unsigned multiply accumulate, and signed multiply accumulate operations. the type of operation is selected by the address the first operand is written to. the hardware multiplier has two 16-bit operand registers, op1 and op2, and three result registers, sumlo, sumhi, and sumext. sumlo stores the low word of the result, sumhi stores the high word of the result, and sumext stores information about the result. 6.12.1 module registers address offset reset value register name size 0x10 0x0000 mpy (operand 1) 16 0x12 0x0000 mpys (operand 1) 16 0x14 0x0000 mac (operand 1) 16 0x16 0x0000 macs (operand 1) 16 0x18 0x0000 operand 2 16 0x1a 0x0000 sumlo 16 0x1c 0x0000 sumhi 16 0x1e 0x0000 sumext 16 table 6.12.1.1 : multiplier module registers register mpy (0x10) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : operand 1 unsigned multiply table 6.12.1.2 : mpy register mpys (0x12) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : operand 1 signed multiply this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 53 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 table 6.12.1.3 : mpys register mac (0x14) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : operand 1 unsigned multiply accumulate table 6.12.1.4 : mac register macs (0x16) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : operand 1 signed multiply accumulate table 6.12.1.5 : macs register operand 2 (0x18) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 content 15:0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w rv r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : operand 2 (write access starts multiplication) table 6.12.1.6 : operand 2 register sumlo (0x1a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : lower 16 bit of result table 6.12.1.7 : sumlo this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 54 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register sumhi (0x1c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : in case of operation: mpy: upper 16 bit of result mpys: the msb is the sign of the result. the remaining bits are the upper 15-bits of the result. two's complement notation is used for the result. mac: upper 16 bit of result macs: upper 16-bits of the result. two's complement notation is used for the result. table 6.12.1.8 : sumhi register sumext (0x1e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 15:0 : in case of operation: mpy: always 0x0000 mpys: contains the extended sign of the result 0x0000 if result was positive 0xffff if result was negative mac: contains the carry of the result 0x0000 no carry result 0x0001 result with carry mpys: contains the extended sign of the result 0x0000 if result was positive 0xffff if result was negative table 6.12.1.9 : sumext 6.13 timer0 (window-watchdog) timer1 ? two 32bit width decrementing timers ? 32bit little endian atomic read or write over 16bit data bus ? timer 0 is used as watchdog, so it triggers a system reset instead of an interrupt ? timer reset window support 6.13.1 module registers address offset reset value register name size 0x00 0xffff.ffff timer value 32 0x04 0xffff.ffff timer counter 32 0x08 0x0000 timer control 16 0x0a 0x001f timer window config 16 0x0c - timer interrupt clear 16 this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 55 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 table 6.13.1.1 : timer 0 and timer 1 module registers register timer value (0x00) bit 31 30 29 28 27 16 25 24 23 22 21 20 19 18 17 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 internal access r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w external access r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w r / w bit description 31:0 : timer start value table 6.13.1.2 : timer value register timer counter (0x04) bit 31 30 29 28 27 16 25 24 23 22 21 20 19 18 17 6 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 internal access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r bit description 31:0 : current timer value table 6.13.1.3 : timer counter register timer control (0x08) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r r r r r/w (r) w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r r r r r/w (r) w r/w r/w bit description 15:8 : password must be written as 0xa5 will always be read as 0x96 3 : clock base selector (timer 1 only) 0 - mclk 1 C mclk/(16*baud rate) synchronize timer to spi clock 2 : timer reset 0 - no influence 1 - reset to start value 1 : loop 0 - run once and hold afterwards (clears "run enable") 1 - loop 0 : run enable 0 - timer stopped 1 - timer enabled table 6.13.1.4 : timer control this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 56 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register timer window config (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 internal access r/w r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r r r/w r/w r/w r/w r/w r/w bit description 15:8 : timer window config (only applicable for window-watchdog) password must be written as 0xa5 will always be read as 0x96 5 : window enable 0 - no window (default) 1 - window active 4:0 : window size reset window is defined as: timer value < (2^window size - 1) table 6.13.1.5 : timer window config register timer interrupt clear (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - - w w external access - - - - - - - - - - - - - - w w bit description 1 : timer irq clear 0 - no influence 1 - clear interrupt 0 : window irq clear 0 - no influence 1 - clear interrupt table 6.13.1.6 : timer interrupt clear this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 57 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.14 spi module ? can be used as master or salve ? the spi interface consists of the following 4 signals: ? sck: spi clock (driven by master) ? csb: low active chip select (driven by master) ? miso: master in, slave out (data from slave to master) ? mosi: master out, slave in (data from master to slave) ? configurable phase, polarity and bit order ? byte and multi-byte transfer support ? slave mode spi clock monitoring (time out) ? 4 data word transmit and receive fifos figure 6.14-1 : spi timing diagram 6.14.1 spi module registers address offset reset value register name size 0x00 0x0000 transmit data / receive data 16 0x02 0x2009 control 16 0x04 0x0000 baud config 16 0x06 0xffff time out config 16 0x08 - module reset 16 0x0a - status 16 0x0c - error 16 0x0e - interrupt clear 16 table 6.14.1.1 : spi module registers this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 58 / 67 qm-no.: 25ds0014e.00 last bit sample data sscph 0 1 0 1 1st edge: shift 2nd edge: sample sscpo 0 0 1 1 off level: 0 off level: 1 off level: 1 off level: 0 first bit apply data mosi/miso mosi/miso apply data apply data sample data sample data apply data apply data sample data 1st edge: sample 2nd edge: shift 1st edge: shift 2nd edge: sample 1st edge: sample 2nd edge: shift
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register transmit data / receive data (0x00) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r (r) w r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r (r) w r/w r/w r/w r/w r/w r/w r/w r/w bit description 8 : csb control (only for data transition and in master mode) 0 - byte mode 1 - keep csb active after related byte was transmitted 7:0 : transmit data / receive data the 'send low water' interrupt will be cleared by writing a byte to the transmit data register (fifo). the 'receive high water' interrupt will be cleared by reading a byte from the receive data register (fifo). (see list of all interrupts) table 6.14.1.2 : transmit data / receive data register control (0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 internal access r r/w r/w r/w r r/w r/w r/w r r r r r/w r/w r/w r/w external access r r/w r/w r/w r r/w r/w r/w r r r r r/w r/w r/w r/w bit description 14:12 : high water receive fifo level interrupt will be asserted when receive fifo fill level increases to this value default value: 2 10:8 : low water transmit fifo level interrupt will be asserted when transmit fifo fill level decreases to this value default value: 0 3 : slave 0 - master 1 - slave 2 : polarity: sscpo, see spi mode diagram 0 - clock off level 0 1 - clock off level 1 1 : phase: sscph, see spi mode diagram 0 - 1st edge shift, 2nd edge sample 1 - 1st edge sample, 2nd edge shift 0 : order 0 - lsb first 1 - msb first table 6.14.1.3 : control register baud config (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w rv r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 59 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit description 15:0 : baud divider = (system clock frequency) / (2 * baud rate) note: minimal value for baud divider is 4 table 6.14.1.4 : baud config register timeout config (0x06) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 internal access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w external access r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description 15:0 : timeout value maximum allowed count of system clock cycles between 2 spi clock edges table 6.14.1.5 : timeout config register module reset (0x08) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - w w w external access - - - - - - - - - - - - - w w w bit description 2 : spi module reset 1 : receive fifo clear 0 : transmit fifo clear table 6.14.1.6 : module reset register status (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 6:4 : receive fifo level 2:0 : transmit fifo level table 6.14.1.7 : status this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 60 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register error (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 1 : transmit fifo was empty (only in slave mode) will be cleared on read 0 : receive fifo was full (received data will be lost) will be cleared on read table 6.14.1.8 : error register interrupt clear (0x0e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - - - - - - - w w external access - - - - - - - - - - - - - - w w bit description 1 : clear error irq 0 : clear timeout irq table 6.14.1.9 : interrupt clear this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 61 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.15 gpio module ? up to 6 gpios ? interrupt capable (configurable for positive and / or negative signal edge interrupt) 6.15.1 gpio module registers address offset reset value register name size 0x00 0x0000 output data 16 0x02 0x003f direction 16 0x04 - input data 16 0x06 0x0000 posedge interrupt enable 16 0x08 - posedge interrupt status 16 0x0a - posedge interrupt clear 16 0x0c 0x0000 negedge interrupt enable 16 0x0e - negedge interrupt status 16 0x10 - negedge interrupt clear 16 0x12 0x0000 port config 16 table 6.15.1.1 : gpio module registers register output data (0x00) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit description 7:0 : output data reset value: 0x0000 table 6.15.1.2 : output data register direction (0x02) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 internal access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit description 7:0 : direction 0 - output, pull down disabled 1 - input, pull down enabled reset value: 0x00ff table 6.15.1.3 : direction this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 62 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register input data (0x04) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 7:0 : input data reset value: 0x0000 table 6.15.1.4 : input data register posedge interrupt enable (0x06) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit description 7:0 : enable 0 - disabled 1 - a positive edge on related "input data" bit will set interrupt bit reset value: 0x0000 table 6.15.1.5 : posedge interrupt enable register posedge interrupt status (0x08) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 7:0 : status 0 - no interrupt 1 - interrupt was asserted reset value: 0x0000 table 6.15.1.6 : posedge interrupt status register posedge interrupt clear (0x0a) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - w w w w w w w w external access - - - - - - - - w w w w w w w w bit description 7:0 : clear 0 - no influence 1 - clears related interrupt bit table 6.15.1.7 : posedge interrupt clear this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 63 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 register negedge interrupt enable (0x0c) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w external access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit description 7:0 : enable 0 - disabled 1 - a negative edge on related "input data" bit will set interrupt bit reset value: 0x0000 table 6.15.1.8 : negedge interrupt enable register negedge interrupt status (0x0e) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r r external access r r r r r r r r r r r r r r r r bit description 7:0 : status 0 - no interrupt 1 - interrupt was asserted reset value: 0x0000 table 6.15.1.9 : negedge interrupt status register negedge interrupt clear (0x10) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value - - - - - - - - - - - - - - - - internal access - - - - - - - - w w w w w w w w external access - - - - - - - - w w w w w w w w bit description 7:0 : clear 0 - no influence 1 - clears related interrupt bit table 6.15.1.10 : negedge interrupt clear register port config (0x12) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 internal access r r r r r r r r r r r r r r r/w r/w external access r r r r r r r r r r r r r r r/w r/w bit description 1:0 : io port config for details see io port multiplexer reset value: 0x0000 table 6.15.1.11 : port config this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 64 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 6.15.2 io port multiplexer table 6.15.2.1 : io port multiplexer ? "port config" register (cfg) is located in gpio module ? test mode default: pull down ? io port default: gpio input and pull down this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 65 / 67 qm-no.: 25ds0014e.00 io port test mode normal mode cfg[0] = 0 cfg[0] = 1 tmode 1 0 0 io0 gpio00 gpio00 gpio00 io1 gpio01 gpio01 gpio01 io2 tdo gpio02 sck io3 tdi gpio03 miso io4 tms gpio04 mosi io5 tck gpio05 csb
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 7 robustness 7.1 esd the esd protection circuitry is measured according to aec-q100-002 with the following conditions: test method (hbm): ? vin = 2000 v (according to device class h1c) ? rext = 1500 ohm ? cext = 100 pf test method (cdm): ? vin = 500 v for all pins ? vin = 750 v for corner pins 7.2 latch up test test method: ? 100 ma positive and negative pulses at 85 c according to aec-q100-004. 8 package 8.1 marking 8.1.1 top side elmos e909.05a xxx#lyww*@ where e / m / t volume production / prototype / test circuit 000.01 elmos project number a elmos project revision code xxx production lot number # assembler code l production line code yww year and week of assembly * mask revision code @ elmos internal code this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 66 / 67 qm-no.: 25ds0014e.00
halios? multi-purpose optical sensor with high light immunity e909.05 preliminary information aug 02, 2011 warning C life support applications policy elmos semiconductor ag is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the respons - ibility of the buyer, when utilizing elmos semiconductor ag products, to observe standards of safety, and to avoid situations in which malfunction or failure of an elmos semiconductor ag product could cause loss of human life, body injury or damage to property. in development your designs, please ensure that elmos semiconductor ag products are used within specified operating ranges as set forth in the most recent product specifications. general disclaimer information furnished by elmos semiconductor ag is believed to be accurate and reliable. however, no responsibility is assumed by elmos semiconductor ag for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of elmos semiconductor ag. elmos semi - conductor ag reserves the right to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability . application disclaimer circuit diagrams may contain components not manufactured by elmos semiconductor ag, which are included as means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. the information in the application examples has been carefully checked and is believed to be entirely reliable. how - ever, no responsibility is assumed for inaccuracies. furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of elmos semiconductor ag or others. contact information headquarters elmos semiconductor ag heinrich-hertz-str. 1 ? d-44227 dortmund (germany) +492317549100 : sales@elmos.de : www.elmos.de regional sales and application support office munich elmos semiconductor ag am geflgelhof 12 ? 85716 unterschlei?heim/eching +4989 3183700 sales office france elmos france sas 9/11 alle de l'arche ? la dfense ? 92671 courbevoie cedex (france) +33149971591 sales and application support office north america elmos na. inc. 32255 northwestern highway, suite 45 ? farmington hills, mi 48334 +12488653200 sales and application support office korea and japan elmos korea dongbu root building, 16-2, suite 509, ? sunae-dong, bundang-gu, seongnam-shi, kyonggi-do (korea) +82317141131 sales and application support office china elmos semiconductor technology (shanghai) co., ltd. 57-01e, lampl business centre, 57f, the exchange ? 1486 nanjing w rd. (299 tongren rd) ? jingan shanghai ? p.r.china 200040 +862161717358 sales and application support office singapore elmos semiconductor singapore pte ltd. 60 alexandra terrace ? #09-31 the comtech ? singapore 118502 +6566351141 ? elmos semiconductor ag, 2011. reproduction, in part or whole, without the prior written consent of elmos semiconductor ag, is prohibited. this document contains information on a pre-production product. elmos semiconductor ag reserves the right to change specifications and information herein without notice. elmos semiconductor ag data sheet 67 / 67 qm-no.: 25ds0014e.00

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